With continued pressure to make increasingly dense devices, the semiconductor device industry is switching to the use of three dimensional (3D) memory structures. For instance, NAND flash memory has moved from a planar configuration to a vertical configuration (VNAND). This vertical configuration permits the memory devices to be formed at significantly greater bit density. In manufacturing stacking of 3D semiconductor chips, stair-like structures are often utilized to allow multiple interconnection structures to be disposed thereon, forming high-density of vertical transistor devices. An inter-level dielectric (ILD) may be disposed over the stair-like structure between interconnection levels to isolate conductor layers disposed in interconnection levels. However, due to physical stress within the inter-level dielectric that may be caused by thermal expansion difference between the inter-level dielectric and the interconnection levels, cracks or defects are often introduced into the semiconductor chips, affecting the overall performance of the device.
Therefore, there is a need in the art to provide an improved method that inhibits the occurrence of cracks and defects in the semiconductor chips.